1. Field of the Invention
The present invention relates to a memory cell array structure comprising a number of memory cells having a structure adapted to attain a high scale of integration, and to a process for producing the same.
2. Prior Art
A high scale of integration of a memory cell array structure enables various electronic appliances such as information processing appliances to be miniaturized and improved in performance. Accordingly, intensive investigations have been made with a view to scaling up the integration of a memory cell array structure.
A brief description will be made of a few types of memory cell structures incorporated into conventional memory cell array structures of dynamic random access memory (DRAM) type as examples.
Memory cells constituting a memory cell array structure of DRAM type each comprise one switching element and one capacitor. Such memory cells are widely used since they are adapted to attain a high scale of integration. In each such memory cell, a switching transistor is used to store an electric charge in a capacitor or discharge an electric charge from the capacitor to thereby provide a certain level of an electric charge being present in the capacitor, which level corresponds to a certain piece of information.
In general, such a memory cell has a built-in structure wherein a capacitor comprising a silicon substrate, an insulating film (e.g., a silicon oxide film) and a polycrystalline silicon film is juxtaposed in a plan with a MOS transistor around the upper surface of the silicon substrate. In the case of this type of memory cell structure, however, since the area occupied by one memory cell as projected on the reverse surface of a substrate is large, the scale of integration in the production of a memory cell array structure comprising a number of such memory cells is inevitably restricted. Therefore, the above-mentioned type of memory cell structure is not preferable in order to scale up the integration of a memory cell array structure. In view of this, there has heretofore been proposed various memory cell array structures having a three-dimensional structure, such for example as will now be described while referring to FIGS. 1 to 3, wherein hatching to indicate cross sections, and the like are partially omitted to avoid too much complication of the drawings.
FIG. 1 is a schematic cross-sectional view of a conventional memory cell structure adapted to attain a high scale of integration in a memory cell array structure.
This memory cell structure comprises a so-called "trench capacitor" 15 formed by utilizing a trench 13 dug in a silicon substrate 11, and a switching transistor 25 constituted of a drain region 19 connected with a bit line 17, a gate electrode 21 as a word line, and a source electrode (not shown in FIG. 1) connected with the cell plate of the capacitor 15. According to this memory cell structure, the area occupied by the capacitor portion as projected on the reverse surface of the substrate can be decreased to enable a memory cell array structure to be greatly improved in the scale of integration of memory cells incorporated thereinto.
FIGS. 2 and 3 are schematic fragmentary cross sectional views of conventional memory cell array structures comprising a number of memory cells better adapted to attain a high scale of integration.
FIG. 2 shows part of a memory cell array structure as disclosed in Japanese Patent Laid-Open No. 239,658/1986. This memory cell array structure comprises a p.sup.+ -type silicon substrate 31; a plurality of insular p.sup.- -type semiconductor layers 35 provided thereon and separated from one another by a first trench 33 provided therebetween in matrix fashion and having an inner wall face having thereon an insulating layer 39; a capacitor electrode 37 embedded in a second trench formed inside the first trench by the insulating film 39 and ranging from the bottom to part of the height of the second trench; a plurality of n.sup.- -type semiconductor layers 41 embedded in lower inner side wall portions of respective insular p.sup.- -type semiconductor layers 35 and substantially confronting the capacitor electrode 37 through the insulating film 39 therebetween; a plurality of gate electrodes 43 embedded in the second trench on the upper side of the capacitor electrode 37 with the insulating layer 39 therebetween; a plurality of n.sup.+ -type semiconductor layers 45 covering the upper surface of the insular p.sup.- -type semiconductor layers 35; and p.sup. - -type semiconductor regions 47 constituting upper inner side wall portions of the respective insular p.sup.- -type semiconductor layers. The capacitor of each memory cell comprises part of the capacitor electrode 37, an n.sup.- -type semiconductor layer 41 as a partner capacitor electrode, and part of the insulating film 39, while the switching transistor of each memory cell comprises part of a gate electrode 43, part of an n.sup.+ -type semiconductor layer 45 as a drain region, a p.sup.- -type semiconductor region 47 as a channel region, and a source region (not shown in FIG. 1) connected with the n.sup.- -type semiconductor layer 41.
FIG. 3 shows part of a memory cell array structure as disclosed in IEEE, pp. 714-717 (1985). Each memory cell of this memory cell array structure comprises a p.sup.+ -type semiconductor substrate 51 having a p-type semiconductor layer 52 provided thereon and a trench 53 formed therein; a capacitor electrode 55 embedded in the trench 53 with a thin insulating film 57 therebetween (provided on the inner wall face of the trench 53 and substantially corresponding to the contour of the trench 53) and ranging from the bottom to part of the height of the trench 53; a drain region 59 provided on an upper outer side wall face of the trench 53 with an insulating film 58 therebetween and on the upper side of the p-type semiconductor layer 52; a channel region 61 constituting part of the p-type semiconductor layer 52 and existing along an upper outer side wall face of the trench 53 with the insulating film 58 therebetween but under the drain region 59; a source region 63 provided on an upper outer side wall face of the trench 53 with the insulating film 58 therebetween but under the channel region 61 and embedded in the p-type semiconductor layer 52; and a gate electrode 65 partially inserted into the trench 53 and substantially confronting the channel region 61. The capacitor of each memory cell comprises the capacitor electrode 55 and part of the p.sup.+ -type semiconductor substrate as a partner capacitor electrode, while the switching transistor of each memory cell comprises the drain region 59, the channel region 61, the source region 63, and the gate electrode 65.
Each memory cell of either one of the memory cell array structures as shown in FIGS. 2 and 3 has a capacitor and a switching transistor so three-dimensionally formed by utilizing a trench, particularly the side wall thereof, as to greatly decrease the area occupied by the memory cell as projected on the upper surface of a substrate. Therefore, the use of such a memory cell structure in the production of a memory cell array structure of DRAM type can attain a higher scale of integration than the use of a memory cell structure as shown in FIG. 1.
In the case of the conventional memory cell array structure as shown in FIG. 2, however, an anisotropic etching technique is employed to form gate electrodes on the inside and along the side walls of the second trench, resulting in a cell-to-cell variation in channel length, which is problematic in that the operational characteristics differ from switching transistor to switching transistor.
The conventional memory cell array structure as shown in FIG. 3 involves not only a problem as mentioned above that differences in the operational characteristics between switching transistors are caused by a cell-to-cell variation in channel length, but also problems that leaks of electric current are liable to occur between adjacent capacitors and that it is not easy to form electroconductive side portions connecting transistor portions with respective capacitor portions.
Further, in either one of the memory cell array structures as shown in FIGS. 2 and 3, the capacity is liable to differ from capacitor to capacitor because of cell-to-cell variations in the depth of trench and the depth of capacitor electrode embedded in a trench.